1. Field of the Invention
The present invention relates to memory devices and, more particularly, to non-volatile latches that operate as memory devices.
2. Description of the Related Art
Semiconductor memories are well known and can be classified as either volatile or non-volatile memory. Volatile memory loses stored information (data) once power is removed, while non-volatile memory retains its stored information even after power is removed.
One common type of semiconductor memory that is non-volatile is known as a non-volatile latch. A single non-volatile latch provides information storage for one-bit of data through use of a pair of cross-coupled drive transistors which each have a load. The load for each of the drive transistors is typically a transistor but can also be a non-active device such as a resistor. Non-volatile latches also provide a continuous status output signal and thus do not require read amplifiers or refresh operations.
FIG. 1 is a schematic diagram of a conventional non-volatile latch circuit 100. The non-volatile latch circuit 100 is a complementary metal-oxide-semiconductor (CMOS) circuit having n-type metal-oxide-semiconductor (NMOS) devices and p-type metal-oxide-semiconductor (PMOS) devices. The non-volatile memory circuit 100 includes a first floating-gate NMOS transistor 101 and a second floating-gate NMOS transistor 102. The NMOS transistor 101 and the second NMOS transistor 102 each operate as a memory cell. The non-volatile memory circuit 100 also includes a first PMOS transistor 104 and a second PMOS transistor 106. The first PMOS transistor 104 serves as a load for the first floating-gate NMOS transistor 101, and the second PMOS transistor 106 serves as a load for the second floating-gate NMOS transistor 102. Additionally, the non-volatile latch circuit 100 may also include an inverter 108 to buffer the data stored in the non-volatile latch and thus provide a voltage output (VOUT) for the memory bit.
Conventional non-volatile latches are programmed to store data and then retain the data until subsequently reprogrammed or cleared. Unfortunately, however, when programming is weak or leakage currents are present, non-volatile latches are significantly more likely to fail and thus lose the stored data. Although the programming of stored data can be verified after programming in a digital sense (i.e., xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d), conventionally there exists no way to conveniently examine program strength (e.g., program charge) of non-volatile latches. As a result, non-volatile latches with weak programming or significant leakage currents are normally not identified and thus used without knowledge of being susceptive to failure.
Thus, there is a need for improved approaches to examining program strength of non-volatile latches.
Broadly speaking, the invention relates to an improved approach to examining program strength of non-volatile latches. The program strength is able to be evaluated by inferring floating gate charge of memory elements of the non-volatile latches as indicated by current characteristics of the memory elements. Access to the memory elements current characteristics is facilitated by monitoring circuitry provided integral with the non-volatile latches.
The invention can be implemented in numerous ways including as a method, a system, and a device. Several embodiments of the invention are discussed below.
As a non-volatile memory circuit, one embodiment of the invention includes at least: a non-volatile memory cell capable of being programmed into a programmed state; a monitoring circuit operatively connected to the non-volatile memory cell, the monitoring circuit being configured to measure strength of the programming of the non-volatile memory cell in the programmed state; and a buffer configured to output an output signal in accordance with the programmed state of the non-volatile memory cell.
As a non-volatile memory circuit, another embodiment of the invention includes at least: a non-volatile memory cell capable of being programmed into a programmed state; means for measuring strength of the programming of the non-volatile memory cell in the programmed state; and a buffer configured to output an output signal in accordance with the programmed state of the non-volatile memory cell.
As a non-volatile memory circuit, still another embodiment of the invention includes at least: a first floating gate transistor having a drain terminal, a source terminal, a control gate terminal, and a charge injection terminal, the drain terminal being coupled to a first node, the source terminal being coupled to a first potential, the gate terminal being coupled to a first set potential, and the charge injection terminal being coupled to a second set potential; a second floating gate transistor having a drain terminal, a source terminal, a control gate terminal, and a charge injection terminal, the drain terminal being coupled to a second node, the source terminal being coupled to the first potential, the gate terminal being coupled to the second set potential, the charge injection terminal being coupled to the first set potential; a first latch transistor having a drain terminal, a source terminal and a gate terminal, the drain terminal being coupled to the first node, the source terminal being coupled to a second potential, and the gate terminal being coupled to the second node; a second latch transistor having a drain terminal, a source terminal and a gate terminal, the drain terminal being coupled to the first node, the source terminal being coupled to the second potential, and the gate terminal being coupled to the first node; a first test transistor having a drain terminal, a source terminal and a gate terminal, the drain terminal being coupled to the first node, the source terminal being coupled to a first test line, and the gate terminal being coupled to a second test line; a second test transistor having a drain terminal, a source terminal and a gate terminal, the drain terminal being coupled to the second node, the source terminal being coupled to the first test line, and the gate terminal being coupled to a third test line; and an output buffer coupled to the second node for providing an output of the non-volatile memory circuit.
As a method for examining program strength of a previously programmed non-volatile memory latch provided within an integrated circuit, one embodiment of the invention includes the acts of: setting external test control signals that provide electrical connection to the non-volatile memory latch; and determining a programming strength for the non-volatile memory latch via the electrical connection provided to the non-volatile memory latch.
As an integrated circuit, one embodiment of the invention includes at least: a first non-volatile latch providing a pair of first memory cells that together provide a first bit of memory; a first pair of test selectors respectively controllably coupled to the pair of the first memory cells; a second non-volatile latch providing a pair of second memory cells that together provide a second bit of memory; a second pair of test selectors respectively controllably coupled to the pair of the second memory cells; a third non-volatile latch providing a pair of third memory cells that together provide a third bit of memory; a third pair of test selectors respectively controllably coupled to the pair of the first memory cells; a first test line operatively connected to the first pair of test transistors; a second test line operatively connected to one of the test selectors of the first pair of transistors; and a third test line operatively connected to another of the test selectors of the first pair of transistors.
The advantages of the invention are numerous. Different embodiments or implementations may yield one or more of the following advantages: One advantage of the invention is that programming margin can be conveniently examined. Another advantage of the invention is that program strength can be determined based on a quantitative examination of program charge. Yet another advantage of the invention is that reliability or failure testing of non-volatile latches is facilitated. Such testing can, for example, allow for rejection of defective non-volatile latches, determining end of programming life or program strength over time, or determining need for refresh programming. Other aspects and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings which illustrate, by way of example, the principles of the invention.